UPSD3233 データシートの表示（PDF） - STMicroelectronics

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UPSD3233

Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM

STMicroelectronics 

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

POWER-SAVING MODE

Two software selectable modes of reduced power

consumption are implemented.

Idle Mode

The following Functions are Switched Off.

■ CPU (Halted)

The following Function Remain Active During Idle

Mode.

■ External Interrupts

■ Timer 0, Timer 1, Timer 2

■ DDC Interface

■ PWM Units

■ USB Interface

■ USART

■ 8-bit ADC

■ I2C Interface

Note: Interrupt or RESET terminates the Idle

Mode.

Power-Down Mode

■ System Clock Halted

■ LVD Logic Remains Active

■ SRAM contents remains unchanged

■ The SFRs retain their value until a RESET is

asserted

Note: The only way to exit Power-down Mode is a

RESET.

Table 25. Power-Saving Mode Power Consumption

Mode

Addr/Data

Ports1,3,4

PWM

Idle

Maintain Data

Maintain Data

Active

Power-down Maintain Data

Maintain Data

Disable

I2C

Active

Disable

DDC

Active

Disable

USB

Active

Disable

Power Control Register

The Idle and Power-down Modes are activated by software via the PCON register.

Table 26. Pin Status During Idle and Power-down Mode

SFR Reg

Addr Name

7

Bit Register Name

6

5

4

3

2

1

87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD

0

IDLE

Reset

Value

Comments

00 Power Ctrl

Table 27. Description of the PCON Bits

Bit

Symbol

Function

7

SMOD Double baud data rate bit UART

6

SMOD1 Double baud data rate bit 2nd UART

5

LVREN LVR disable bit (active High)

4

ADSFINT Enable ADC Interrupt

3

RCLK1(1) Received clock flag (UART 2)

2

TCLK1(1) Transmit clock flag (UART 2)

1

PD

Activate Power-down Mode (High enable)

0

IDL

Activate Idle Mode (High enable)

Note: 1. See the T2CON register for details of the flag description

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