UPSD3253B-40 データシートの表示（PDF） - STMicroelectronics

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UPSD3253B-40

Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM

STMicroelectronics 

µPSD325X DEVICES

Figure 85. Reset (RESET) Timing

VCC

RESET

VCC(min)

tNLNH-PO

Power-On Reset

tOPR

tNLNH

tNLNH-A

Warm Reset

tOPR

AI02866b

Table 135. Reset (RESET) Timing (5V Devices)

Symbol

Parameter

Conditions

Min

tNLNH

RESET Active Low Time 1

150

tNLNH–PO

Power-on Reset Active Low Time

1

tNLNH–A

Warm RESET 2

25

tOPR

RESET High to Operational Device

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Max

Unit

ns

ms

µs

120

ns

Table 136. Reset (RESET) Timing (3V Devices)

Symbol

Parameter

Conditions

Min

tNLNH

RESET Active Low Time 1

300

tNLNH–PO

Power-on Reset Active Low Time

1

tNLNH–A

Warm RESET 2

25

tOPR

RESET High to Operational Device

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Max

Unit

ns

ms

µs

300

ns

Table 137. VSTBYON Definitions Timing (5V Devices)

Symbol

Parameter

Conditions

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Min

Typ

Max Unit

20

µs

20

µs

Table 138. VSTBYON Timing (3V Devices)

Symbol

Parameter

tBVBH

VSTBY Detection to VSTBYON Output High

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Conditions

(Note 1)

(Note 1)

Min

Typ

Max Unit

20

µs

20

µs

166/176

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