VSC7133QU データシートの表示（PDF） - Vitesse Semiconductor

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VSC7133QU

10-bit Transceiver for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Advance Product Information

VSC7133

Table 5: Pin Identification

Pin #

Name

Description

22

23

62, 61

45,44,43,41

40,39,38,36

35,34

19

54, 52

31, 30

24

47

26

16, 17

49

48

55

56

27

18

REFCLKP

REFCLKN

TX+, TX-

R0,R1,R2,R3

R4,R5,R6,R7

R8,R9

EWRAP

RX+, RX-

RCLK,

RCLKN

ENCDET

COMDET

SIGDET

CAP0, CAP1

TCK

TDI

TMS

TRSTN

TDO

VDDA

INPUT - Differential PECL or Single-Ended TTL

This rising edge of this clock latches T(0:9) into the input register. It also provides

the reference clock, at one tenth the baud rate to the PLL. If TTL, connect to

REFCLKP but leave REFCLKN open. If PECL, connect both REFCLKP and

REFCLKN.

OUTPUTS - Differential PECL (AC Coupling recommended)

These pins output the serialized transmit data when EWRAP is LOW. When

EWRAP is HIGH, TX+ is HIGH and TX- is LOW.

OUTPUTS - TTL

10-bit received character. Parallel data on this bus is clocked out on the rising edges

of RCLK and RCLKN. R0 is the first bit received on RX+/RX-.

INPUT - TTL

LOW for Normal Operation. When HIGH, an internal loopback path from the

transmitter to the receiver is enabled and the TX outputs are held HIGH.

INPUTS - Differential PECL (AC Coupling recommended)

The serial receive data inputs selected when EWRAP is LOW. Internally biased to

VDD/2, with 3.3KΩ resistors from each input pin to VDD and GND.

OUTPUT - Complementary TTL

Recovered clocks derived from one twentieth of the RX+/- data stream. Each

rising transition of RCLK or RCLKN corresponds to a new word on R(0:9).

INPUT - TTL

Enables COMDET and word resynchronization when HIGH. When LOW, keeps

current word alignment and disables COMDET.

OUTPUT - TTL

This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains

a Comma Character (‘0011111XXX’). COMDET will go HIGH only during a

cycle when RCLKN is rising. COMDET is enabled by ENCDET being HIGH.

OUTPUT - TTL

SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre

Channel or Gigabit Ethernet signal. A LOW indicates an invalid signal.

ANALOG: Differential capacitor for the CMU’s VCO. 0.1 uF nominal.

INPUT - TTL: JTAG clock input. Not normally connected.

INPUT - TTL: JTAG data input. Not normally connected.

INPUT - TTL: JTAG mode select input. Normally tied to VDDD

INPUT - TLL: JTAG reset input. Tie to VSSD for normal operation.

OUTPU - TTL: JTAG data output. Normally tri-stated.

Analog Power Supply.

Page 14

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52187-0 Rev. 2.4

1/17/00

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