VSC7139TW データシートの表示（PDF） - Vitesse Semiconductor
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VSC7139TW Datasheet PDF : 18 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Pin
R5, P5
R7, P7
P11, R11
P13, R13
D1, D2, E3
E4, C1, C2
C3, B1, B2
B3
A6, B6, C6
D6, A7, D7
A8, B8, C8
D8
B11, A12, B12
C12, D12, B13
C13, D13, A14
B14
C17, D14, D15
D16, D17, E16
E17, F14, F15
F16
T1
E1
E2
A5
B5
C10
D10
B16
B17
U4, U3
U7, U6
U11, U10
U14, U13
N14
Name
Description
TA+, TA-
TB+, TB-
TC+, TC-
TD+, TD-
OUTPUT - Differential PECL (AC Coupling recommended)
These pins output the serialized transmit data for Channel x when PLUP is LOW. When
PLUP is HIGH, Tx+ is HIGH and Tx- is LOW.
RA0, RA1, RA2
RA3, RA4, RA5
RA6, RA7, RA8
RA9
OUTPUT - TTL: 10-bit Receive bus for Channel A. Parallel data on this bus is
synchronous to RCA0 and RCA1. RA0 is the first bit received.
RB0, RB1, RB2
RB3, RB4, RB5
RB6, RB7, RB8
RB9
OUTPUT - TTL: 10-bit Receive bus for Channel B. Parallel data on this bus is
synchronous to RCB0 and RCB1. RB0 is the first bit received.
RC0, RC1, RC2
RC3, RC4, RC5
RC6, RC7, RC8
RC9
OUTPUT - TTL: 10-bit Receive bus for Channel C. Parallel data on this bus is
synchronous to RCC0 and RCC1. RC0 is the first bit received.
RD0, RD1, RD2
RD3, RD4, RD5
RD6, RD7, RD8
RD9
RCM
OUTPUT - TTL: 10-bit Receive bus for Channel D. Parallel data on this bus is
synchronous to RCD0 and RCD1. RD0 is the first bit received.
INPUT - TTL: Recovered clock MODE control. When LOW, RCx0/RCx1 is 1/20th of the
incoming baud rate. When HIGH, RCx0/RCx1 is 1/10th the incoming baud rate.
RCA0
RCA1
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel A at 1/
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RA(0:9) and SYNCA bus.
RCB0
RCB1
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel B at 1/
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RB(0:9) and SYNCB bus.
RCC0
RCC1
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel C at 1/
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RC(0:9) and SYNCC bus.
RCD0
RCD1
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel D at 1/
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RD(0:9) and SYNCD bus.
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
INPUT - Differential PECL (AC Coupling recommended): Serial receive data inputs for
Channel x which are selected when PLUP is LOW. [Internally biased to VDD/2]
PLUP
INPUT - TTL: Parallel Loopback Enable input. Rx is input to the CRU for Channel x
(normal operation) when PLUP is LOW. When HIGH, internal loopback paths from Tx
to Rx are enabled. Refer to Table 2.
G52196-0, Rev 3.3
5/14/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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