W25P022A データシートの表示（PDF） - Winbond

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W25P022A

64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Winbond 

W25P022A

Timing Waveforms, continued

Write Cycle Timing

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[4:1]

CE1

CE2

CE3

Single Write

TADSS

TADSH

Burst Write

TCYC

TKH TKL

Write

Unselected

ADSP is blocked by CE1 inactive

TADCS TADCH

TADVS

TADVH

ADSC initiated write

TAS TAH ADV must be inactive for ADSP write

WR1

WR2

WR3

TWS TWH

GWE allows processor address (and BE=BW)

to be pipelined during a writeback

TWS TWH

TCES

TWS TWH

WR1

TCEH

WR2

WR3

CE1 masks ADSP

TCES TCEH

CE2 and CE3 only sampled with ADSP or ADSC

TCES TCEH

Unselected with CE2

OE

Data-Out

High-Z

Data-In

High-Z

TDS TDH

1a

DON'T CARE

UNDEFINED

BW[4:1] are applied only to first cycle of WR2

2a

2b

2c

2d

3a

- 11 -

Publication Release Date: September 1996

Revision A1

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