25Q128BVCA データシートの表示（PDF） - Winbond

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25Q128BVCA

3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q128BV

7.2.7 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to

a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the

DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon

completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page

Program, Sector Erase, Block Erase and Chip Erase instructions.

Write Disable instruction can also be used to invalidate the Write Enable for Volatile Status Register

instruction.

/CS

CLK

Mode 3

Mode 0

DI

(IO0)

DO

(IO1)

01234567

Mode 3

Mode 0

Instruction (04h)

High Impedance

Figure 6. Write Disable Instruction Sequence Diagram

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Publication Release Date: April 01, 2011

Revision E

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