W83194BR-648 データシートの表示（PDF） - Winbond

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W83194BR-648

CLOCK GENERATOR FOR SIS P4 SERIES CHIPSET

Winbond 

W83194BR-648

9.3 Skew Group Timing Clock

VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V ±5 %, TA = 0°C to +70°C, Cl = 10pF

PARAMETER

MIN. TYP. MAX. UNITS

TEST CONDITIONS

CPU to SDRAM Skew

-2

0

2

nS

CPU Crossing point to SDRAM at

1.5V

CPU (early) to AGP Skew 1

2

4

nS CPU Crossing point to AGP at 1.5V

CPU (early) to ZCLK Skew 1

2

4

nS CPU Crossing point to ZCLK at 1.5V

CPU (early) to PCI Skew

1

2

4

nS CPU Crossing point to PCI at 1.5V

CPU to CPU Skew

150 pS Crossing point

AGP to AGP Skew

175 pS Measured at 1.5V

ZCLK to ZCLK Skew

175 pS Measured at 1.5V

PCI to PCI Skew

500 pS Measured at 1.5V

48 MHz to 48 MHz Skew

1000 pS Measured at 1.5V

REF to REF Skew

500 pS Measured at 1.5V

9.4 CPU 0.7V Electrical Characteristics

VDDA = VDDC= 3.3V ±5 %, TA = 0°C to +70°C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475,

IRE = 2.32mA, Ioh = 6*IREF

PARAMETER

MIN. MAX. UNITS

TEST CONDITIONS

Rise Time

175 700 pS 100 to 200 MHz

Fall Time

175 700 pS 100 to 200 MHz

Absolute Crossing Point Voltages 250 550 mV 100 to 200 MHz

Cycle to Cycle jitter

125 pS 100 to 200 MHz

Duty Cycle

45 55

% 100 to 200 MHz

9.5 CPU 1.0V Electrical Characteristics

VDDA = VDDC= 3.3V ±5 %, TA = 0°C to +70°C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.2V, Voh = 0.8V, Vr = 221,

IREF = 5.0 mA, Ioh = 4*IREF

PARAMETER

Rise Time

MIN. MAX. UNITS

TEST CONDITIONS

300 600 pS 100 to 200 MHz

Fall Time

300 600 pS 100 to 200 MHz

Absolute Crossing Point Voltages 510 760 mV 100 to 200 MHz

Cycle to Cycle Jitter

200 pS 100 to 200 MHz

Duty Cycle

45 55

% 100 to 200 MHz

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