WM2638 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM2638

Dual 12-Bit Serial Input Voltage Output DAC with Internal reference

Wolfson Microelectronics plc 

WM2638

DEVICE DESCRIPTION

Production Data

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference

input voltage and the input code according to the following relationship:

Output voltage = ( ) 2 VREF CODE

4096

1111

INPUT

1111

1111

1000

:

0000

0001

1000

0000

0000

0111

1111

1111

0000

:

0000

0001

0000

0000

0000

OUTPUT

( ) 4095

2 VREF

4096

:

( ) 2049

2 VREF

4096

( ) 2048

2 VREF

= VREF

4096

( ) 2047

2 VREF

4096

:

( )1

2 VREF

4096

0V

Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a

2kΩ load with a 100pF load capacitance.

SERIAL INTERFACE

When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data

clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input

register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers

the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register

(see Table 2).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

fSCLKmax =

1

tWCH min + tWCL min

= 20MHz

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC

settling time to 12 bits limits the update rate for large input step transitions.

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 99

7

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