WM8143-12
Detailed Timing Diagrams
Production Data
MCLK
VSMP, RLC
tDSU
R,G,B Video Inputs
(Default Mode)
R,G,B Video Inputs
(CDSREF[1]=0,CDSREF[0]=0)
R,G,B Video Inputs
(CDSREF[1]=0,CDSREF[0]=1)
R,G,B Video Inputs
(CDSREF[1]=1,CDSREF[0]=0)
R,G,B Video Inputs
(CDSREF[1]=1,CDSREF[0]=1)
tDH
tVSU tVH
tVSU tVH
tVSU tVH
tVSU tVH
Figure 18 Detailed Video Input Timing - Modes 1 and 2
tRSU
tRH
tRSU
tDSU
tRH
tRSU
tRH
tRSU
tDH
tVSU tVH
tVSU tVH
tVSU tVH
tVSU tVH
tVSU tVH
tRH
MCLK
tDSU
VSMP, RLC
R,G,B Video Inputs
(CDSREF[1]=0,CDSREF[0]=0)
Figure 19 Detailed Video Input Timing - Mode 3
MCLK
tDSU
VSMP, RLC
R,G,B Video Inputs
RESET
VIDEO
tDH
tDSU
tVSU tVH
tRSU
tDH
tVSU
tVH
tVSU
tVH
tDH
tVSU tVH
tRH
Figure 20 Detailed Video Input Timing - Mode 4
Wolfson Microelectronics
20
PD. Rev 4 Nov. 99