WM8783 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8783

Stereo Low Power 96kHz ADC

Wolfson Microelectronics plc 

Production Data

AUDIO INTERFACE TIMING

LRCLK (input)

WM8783

BCLK (see note)

ADCDAT (output)

tDD

Note – BCLK is generated internally to the WM8783, and is synchronised to LRCLK

Figure 3 Audio Interface Timing

Test Conditions

AVDD = 3.3V, GND = 0V, TA = +25oC.

PARAMETER

Audio Interface Timing

ADCDAT propagation delay from BCLK falling edge

SYMBOL

MIN

TYP

MAX

UNIT

tDD

20

ns

Figure 4 Recommended LRCLK Transition Area for Optimum Performance

It is recommended that for optimum performance the LRCLK transition occurs during the MCLK low,

as shown in Figure 4 above.

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PD, August 2010, Rev 4.0

9

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