WM8971L データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8971L Datasheet PDF : 56 Pages
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WM8971L
Advanced Information
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK = MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
SYMBOL
tBCLKR
tBCLKF
tBCLKDS
tBCLKDS
tDL
tDDA
tDST
tDHT
MIN
10
10
TYP
MAX
3
3
50:50
TMCLKDS
10
10
UNIT
ns
ns
ns
ns
ns
ns
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
ADCLRC/DACLRC set-up time to BCLK rising edge
ADCLRC/DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
Note:
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDD
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
BCLK period should always be greater than or equal to MCLK period.
w
AI Rev 3.0 March 2004
14
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