TMB2193MS100 データシートの表示（PDF） - Fairchild Semiconductor

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TMB2193MS100

Demonstration Board for the TMC2193

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMB2193MS100

CPLD Description

The Altera 10K20 CLPD functions as the central matrix for

routing the buses to the TMC2193. Eight (8) control pins are

connected from port 2 of the MCU to the CLPD. These pins

are used to configure the CPLD and are broken up into 2

buses: FPGA control1 is on pins P2[7:4] and FPGA control2

is on pins P2[3:0]. The 10K20 default configuration routes

the 3 buses from the input edge connector and the bus from

the framestore header to the pixel data (PD[23:0]) port of the

TMC2193. This enables the various input formats of the

TMC2193 to be supported. In addition, the PD input can be

delayed in respect to the HSIN and VSIN for proper data

alignment. Table 2 describes the function of the pixel data

formatting.

Table 2. FPGA Control 1

FGPA

Control1 bit#

3-2

Function

PDMODE

00

01

10

11

1-0

PDDEL

00

01

10

11

Description

PD Input

10-bit format, A bus

20-bit format, C and

B buses

24-bit format, C, A,

and B buses

10-bit format, A bus

delayed

PD delay

0 pxck’s of delay

1 pxck’s of delay

2 pxck’s of delay

3 pxck’s of delay

The FPGA Control 2 bus selects which subcarrier reference

signal to be used; either the GRS from the TMC2072 or the

xRS signal from bus B of the input edge connector. FGPA

Control 2 also selects which set of synchronization signals

are to used; either the IXHSYNC and IXVSYNC from the

input edge connector or the TMC2072 GHSYNC and

GVSYNC.

Table 3. FPGA Control 2

FGPA

Control2 bit#

3-2

1

0

Function

REFSEL

0

1

SYNCSEL

0

1

Description

No Modes

CVBS Input

B[5:2] bus

GENLOCK

HSIN, VSIN Input

IXH and IXV

GH and GV

FPGA Controls 1 and 2 can be accessed by the Raydemo

software. The dialog box exists in the MCU icon of the

TMB2193MS100 window. The functions of these controls

are purposely left generic to allow for the reconfiguration of

the CPLD.

The 10K20 utilization is approximately 20% of the available

logic cells. This allows for additional functions to be

implemented in the 10K20 such as notch filters, interpolation

filters for 4:2:2 to 4:4:4 conversion, simple comb filtering

and ancillary data insertion. These are just some of the

possibilities.

Table 4. Switch, Button, and Jumper Description

Button

MRST

Jumpers

GLOBAL RESET

CASC INT

RBUSEN

Description

Resets the AT89C55. When the GLOBAL RESET jumper is in place, the reset line on all

boards connected to the TMB2193MS100 are driven by MRST.

Description

When GLOBAL RESET is open, only the TMC2193, the TMC2072, the framestore header

and the AT89C55 receive the reset pulse from MRST. When GLOBAL RESET is closed,

the reset line on all boards connected to the TMB2193MS100 are driven by MRST.

Cascade Programming Enable.

When CASC INT is open, the AT89C55 automatically initializes the devices after reset.

When CASC INT is closed, the AT89C55 will wait for a LOW pulse on the PGM_IN pin

before initializing the devices on the TMB2193MS100.

When RBUSEN is open, the RBUS port is disabled.

When RBUSEN is closed, the RBUS port is enabled.

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