X5001 データシートの表示（PDF） - Xicor -> Intersil

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X5001

CPU Supervisor

Xicor -> Intersil 

X5001

Figure 1. Power-Up and Power-Down Timing

VCC

VTRIP

0 Volts

tR

RESET (X5001)

tPURST

tPURST

V TRIP

tF

tRPD

RESET Output Timing

Symbol

Parameter

VTRIP

Reset Trip Point Voltage, X5001PT-4.5A

Reset Trip Point Voltage, X5001PT-4.5

Reset Trip Point Voltage, X5001PT-2.7A

Reset Trip Point Voltage, X5001PT-2.7

Reset Trip Point Voltage, X5001PT-1.8

tPURST

Power-up Reset Timeout

tRPD(5)

VCC Detect to Reset/Output

tF(5)

VCC Fall Time

tR(5)

VCC Rise Time

VRVALID

Reset Valid VCC

Notes: (5) This parameter is periodically sampled and not 100% tested.

PT = Package, Temperature

Figure 2. CS vs. RESET Timing

Min.

4.50

4.25

2.85

2.55

1.70

100

0.1

0.1

1

Typ.

4.63

4.38

2.92

2.63

1.75

200

Max.

4.75

4.50

3.00

2.70

1.80

280

500

Units

V

ms

ns

ns

ns

V

CS

RESET

t CST

t WDO

RESET Output Timing

Symbol

tWDO

tCST

tRST

Parameter

Watchdog Timeout Period,

WD1 = 1, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

CS Pulse Width to Reset the Watchdog

Reset Timeout

tRST

tWDO

Min.

100

450

1

400

100

t RST

Typ.

200

600

1.4

200

Max.

300

800

2

300

Units

ms

ms

sec

ns

ms

12

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