W6PXD3O-0000 データシートの表示（PDF） - Cree, Inc

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W6PXD3O-0000

Silicon Carbide Substrates

Cree, Inc 

Page 10 • Effective December 1998 • Revised March 2003

Standard Specifications

STANDARD SPECIFICATIONS FOR POLISHED SILICON CARBIDE

SUBSTRATES - Surface Finish

Characteristics

Production Grade

Edge Chips/Indents by diffuse

lighting †

None Permitted

Orange Peel/Pits by diffuse lighting*G [ 10% area

Polytype Areas by diffuse lighting* [ 5% area

Striations by diffuse lighting*

3 allowed [ 3mm each

Area Contamination (stains) by high

intensity light

None Permitted

Cracks by high intensity light

Hex Plate by high intensity light*

Scratches by high intensity light*

Masking Defects (Mounds)*

Quantitative by 200X Microscopic

Inspection

Contamination

Quantitative by 200X Microscopic

Inspection

Cumulative Area Defects*

None Permitted

Cumulative area <10%

5 scratches to 1x wafer diameter

cumulative length.

10 defects in 3 or less of the 9

fields inspected in a cross pattern

None in inspected fields

[ 10% area

Research Grade

2 [ 1.5 mm width & depth

[ 30% area

[ 20% area

20 allowed [ 7mm each

None Permitted

None Permitted

Cumulative area <30%

8 scratches to 1.5x wafer diameter

cumulative length.

10 defects in 5 or less of the 9

fields inspected in a cross pattern

None in inspected fields

[ 30% area

Notes:

* Defect limits apply to entire wafer surface except for a 2mm edge exclusion area

G Pits must be < 2mm in distance from one another to be considered a reject cause

† Edge chips must be > 0.5mm on R grade material to be considered a reject cause

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