M65676FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M65676FP

DIGITAL NTSC/PAL ENCODER

MITSUBISHI ELECTRIC  

PRELIMINARY

Notice:This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI ICs (TV)

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

The pixel data interface pin assignment is shown in Table 1.

Table 1 Pixel Data Interface Pin Assignment

Pin name

PXCLK

HD (Note1)

VD (Note1)

PXD [7:0]

PD [7:0]

I/O

Function

Pixel clock output.

O In the case of CCIR656 / CCIR601 8-bit data and CCIR601 16-bit inputs, this will be a free-run clock of 27MHz and

13.5MHz, respectively.

I/O Horizontal sync signal. Input in the slave or output in the master mode.

I/O Vertical sync signal. Input in the slave or output in the master mode.

I

Pixel data input.

8-bit data input in CCIR656 / CCIR601 or the color differential signals (Cb/Cr) input in CCIR601 16-bit data format.

I

Pixel data input.

Luma (Y) data input in CCIR601 16-bit data format.

Note1 : In CCIR656 mode, H sync and V sync generated by EAV will be output via terminals HD and VD, respectively.

OSD Interface

The OSD data, which are storaged in the address assigned by the

color look-up table RAM (CLT-RAM) address data input via OSD

[2:0] ports, are multiplexed into the Y signal synchronizing with OSD

clock (OSDCK) delivered from the M65675FP/M65676FP.

The OSD interface pin assignment is shown in Table 2.

Table 2 The OSD interface Pin assignment

Pin name

OSDCK

OSD [2:0]

I/O

Function

O

OSD clock output.

13.5MHz free-run clock or 6.25MHz H-start-and-stop clock.

I Color look-up table RAM address input.

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