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M65676FP

DIGITAL NTSC/PAL ENCODER

MITSUBISHI ELECTRIC

M65676FP Datasheet PDF : 17 Pages

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PRELIMINARY

Notice:This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI ICs (TV)

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

M65675FP/M65676FP System Architecture

Block Diagram of M65675FP/M65676FP

The M65675FP/M65676FP block diagram is shown in Fig. 3.1.

The M65675FP/M65676FP consists of 4 functional blocks: a video

signal processing, a synchronization control, a serial interface and

an analog signal processing blocks. The video signal processing

block includes an input interface, OSD interface, YCbCr to YUV

converter/encoder and copy protection signal generator (This

function block is M65675FP only).

A sync generator and timing pulse generator are in the

synchronization control block. The serial interface block has an I2C

slave register and command register. The analog signal processing

block includes two 10-bit DACs, a Y/C mixing circuit and three 6-dB

ampliﬁers.

General Description of Each Functional Blocks

◊ Video Signal Processing Block

The Y/Cb/Cr or Y/U/V are converted into digital Y/C signals in

accordance with either NTSC and B/G-PAL standards. In addition

the closed caption, CGMS/WSS and copy protection signals will be

inserted in that digital Y/C signals.

[Input Interface]

The multiplexed Y/Cb/Cr or Y/U/V pixel data are divided by the

individual components, then the Cb/Cr or U/V data rate is increased

from 6.75 Mbps up to 13.5Mbps.

[OSD Interface]

The digital video signal in the CLT (Color Look-up Table) is overlaid

with OSD data according to the external instructions.

[Y/Cb/Cr to Y/U/V Converter]

It converts the Y/Cb/Cr into Y/U/V, and then c-sync and burst signals

are inserted on the converted Y and U/V signals, respectively.

However, the burst insertion is not done in the Y/U/V output mode.

[Encoder]

The closed caption, CGMS/WSS and copy protection signals are

inserted into the Y signal and C signal is modulated into the

appropriate standards. After that processing, both Y and C signals

will be oversampled.

[Copy Protection Processing]

According to the copy protection setting, VBI pulse (AGC and

backporch pulse) and Advanced Split Burst are generated in

accordance with Macrovision Rev 7.01.

◊ Synchronization Control Block

C-sync and several timing control signals for internal use are

generated with 3 different H/V sync signals as reference. 1st

reference H/V sync signal is external input, 2nd is internally

generated one and 3rd is decoded one in digital blanking code

(SAV, EAV etc.)

◊ Serial Interface Block

The registers can be read and written according to I2C bus format.

The data transport to the internal blocks is performed on the trailing

edge of V-sync, except for some set-up registers.

◊ Analog Signal Processing Block

The output of the 10-bit DAC is 1.2VP-P at the sampling frequency

of 27.0MHz. The inputs of Yin and Cin are set up to 0.6VP-P (Typ)

and the component outputs will be ampliﬁed by 6-dB up to 1.2VP-P

(Typ). The analog composite signal from the mixing circuit is also

ampliﬁed up to 1.2VP-P (Typ)

Functional Description

Video Signal processing

Input Interface

Input Format

The video encoder accepts 16/8-bit CCIR601 and CCIR656 format.

The speciﬁcations of these format are described as follows;

◊ 16-bit CCIR601 Interface

PXCLK=13.5MHz

Y=8-bit/13.5Mbps

16-235 straight-binary-data

Cb/Cr=8-bit/13.5 Mbps (Cb=Cr=8-bit/6.75 Mbps)

16-240 128 offset-binary-data

Active video area 525/60=720-pixel¥480 line/frame

(22/284 line-263/525 line)

625/50=720-pixel¥576 line/frame

(23/336 line-310/623 line)

◊ 8-bit CCIR601 Interface

PXCLK=27.0MHz

Cb/Y/Cr=8-bit/27.0Mbps

Y= 8-bit/13.5Mbps