HSP50306 データシートの表示（PDF） - Intersil

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HSP50306

Digital QPSK Demodulator

Intersil 

HSP50306

AC Electrical Specifications 27MHz Clock Rate, VCC = 5.0V ±5%, TA = 0o to 70oC (Note 8)

PARAMETER

SYMBOL

NOTES

MIN

MAX

UNITS

CLK Period

tCP

36

-

ns

CLK High

tCH

12

-

ns

CLK Low

tCL

12

-

ns

Setup RESET to CLK

tRS

15

-

ns

Hold Time RESET to CLK

tRH

1

-

ns

Setup Time DIN0-5 to ADCLK

tDS

9

15

-

ns

Hold Time DIN0-5 to ADCLK

tDH

9

2

-

ns

CLK to DATAOUT, LOCK, AGCOUT

tPD

-

25

ns

Output Rise, Fall Time

tRF

10

-

8

ns

Output Rise, Fall Time (CMOS Outputs)

tTC

10

-

12

ns

NOTES:

8. AC Testing is performed as follows: Input levels 0.0V to 3.0V. Timing reference levels = 1.5V. Output load circuit with CL = 40pF. Output

transition measured at VOH_1.5V and VOL_1.5V.

9. The set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design

and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification

of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D con-

verters for use with the HSP50306.

10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design

changes.

AC Test Load Circuit

DUT

S1

CL

(NOTE)

SWITCH S1 OPEN FOR ICCSB AND ICCOP

NOTE: Test head capacitance

IOH ± 2.5V

IOL

EQUIVALENT CIRCUIT

8-278

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