XRT91L82IB データシートの表示（PDF） - Exar Corporation
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XRT91L82IB Datasheet PDF : 59 Pages
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REV. P1.0.5
PRELIMINARY
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.4
March 2005
1.Renamed RXLCKREF to CDRLCKREF and corrected pin and microprocessor
bit description.
2.Reinstated INTERM pin on E4 to support Single-Ended LVPEL in Hardware
Mode and added INTERM/VCXO_IN pin description.
3.Renamed AVDD1.8_RX, AVDD1.8_TX, VDD1.8 power and VSS ground pin
connections to AVDD_RX, AVDD_TX, VDD_CMOS and GND respectively.
4.Split VDD_IO to VDD_IO and VDD_O and added pin description definition
requiring 1.8V potential for VDD_O in LVDS operation.
5.Added ALTFREQSEL to support lower 77.76/83.31 MHz reference clocks,
INTERM, and SEREFDIS in Host Mode.
6.Corrected LOOPTM_NOJA pin and microprocessor descripton.
7.Redesigned microprocessor registers.
8.Enhanced Section 7.0 Electrical Charateristics.
9.Enhanced Figure 1, “Block Diagram of XRT91L82.
10.Updated Figure 2, “196 BGA Pinout of THE XRT91L82 (Top View).
11.Corrected typos in pin description section and Figure 5, “External Loop Filter.
12.Enhanced Section 3.6 "Clock Multiplier Unit (CMU) and Re-Timer.
13.Updated Figure 14, “Loop Timing Mode Using an External Cleanup VCXO
(Host Mode Only).
P1.0.5
April 2005
1.Changed VDD_O to VDD_IO and removed 1.8V potential requirement for LVDS
operation.
2.Added internal termination and biasing notes in pin descriptions.
3.Moved microprocessor INT pin from C5 to pin D10 and SDO from C6 to pin E9.
4.Corrected REFREQSEL1/SCLK pin from D5 to D12.
5.In Host Mode, Added PRBS_LOCK on pin D4. Added PRBS Lock Interrupt
Enable, Status, and Detection register bits. Added PRBS inversion capability.
6.Moved PRBS Enable register bit from D3 to D4 in register 0x05h.
7.Changed ALTFREQSEL and TXSWING register bit default values to "1."
8.Corrected Transmit Parallel Interface LVDS Operation section and moved to
receive section 2.7.
9.Updated Figure 14 Loop Timing Mode Using an External Cleanup VCXO.
10.Revised and Updated Electrical Characteristics section 7.0
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet April 2005.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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