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MC145149DW データシートの表示(PDF) - Motorola => Freescale

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MC145149DW
Motorola
Motorola => Freescale Motorola
MC145149DW Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
POWER SUPPLY PINS
VDD1, VDD2
Positive Power Supply (Pins 18, 13)
The most positive power supply potentials. Both of these
pins are connected to the substrate of the chip. Therefore,
both must be tied to the same voltage potential. This poten-
tial may range from 3 to 9 V with respect to the VSS pins.
For optimum performance, VDD1 should be bypassed to
VSS1 and VDD2 bypassed to VSS2. That is, two separate
bypass capacitors should be utilized.
VSS1, VSS2
Negative Power Supply (Pins 20, 11)
The most negative power supply potentials. Both of these
pins should be tied to ground.
÷R
LAST BIT INTO
SHIFT REGISTER
÷A
÷N
LAST BIT INTO
SHIFT REGISTER
Figure 7. Bit Stream Formats
fR
REFERENCE
(OSC ÷ R)
fV
FEEDBACK
(fin ÷ N)
PDout
LD
NOTE: The PD output state is equal to either VDD or VSS when active. When not active, the output is high
impedance and the voltage at that pin is determined by the low–pass filter capacitor.
Figure 8. Phase Detector/Lock Detector Output Waveforms
MOTOROLA
MC145149
7

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