Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 1 1 A7 A6
A1 A0
DI
Start Opcode
Bit Bits(2) High - Z
DO
93CS66:
Address bits pattern -> 1-1-1-1-1-1-1-1
Address
Bits(8)
tWP
Ready
Busy
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 0 1 A7 A6
A1 A0
DI
Start Opcode
Bit Bits(2) High - Z
DO
93CS66:
Address bits pattern -> User defined
Address
Bits(8)
tWP
Ready
Busy
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
PRE
;;;;;;;;;
PE
;;;;;;;;;
tCS
CS
SK
1 0 0 A7 A6
A1 A0
DI
Start Opcode
Address
Bit
Bits(2) High - Z Bits(8)
DO
93CS66:
Address bits pattern -> 0-0-0-0-0-0-0-0
tWP
Ready
Busy
NM93CS66 Rev. F.2
12
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