AV90C65N データシートの表示（PDF） - Integrated Circuit Systems

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AV90C65N

Dual Voltage Video/Memory Clock Generator

Integrated Circuit Systems 

ICS90C65

ICS90C65 VGA Interface

The ICS90C65 has two system interfaces: System Bus and

VGA Controller, as well as other programmable inputs. Figure

1 shows how the Integrated Circuit Systems’s VGA Clock

ICS90C65 is connected to a VGA controller. Western Digital

Imaging VGA controllers normally have a status bit that indi-

cates to the VGA controller that it is working with a clock chip.

When working with a clock chip the VGA controller changes

two of its clock inputs to outputs. They are

theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH

outputs and they are used to select the required video frequency.

When the power-down capabilities are used, the control signal

for PWRDN is normally held in one of a group of latches. If

the power-down function is not to be used, PWRDN must be

tied to VDD, otherwise the internal pull-down will place the chip

in the power-down mode.

pull-up at reset

and PR15(5)=0

WD90C26

AMD(3)

VCKIN

MCLK

VCS

VCSEL

LATCH

SD2

SD3

14.318

MHz

ICS90C65

VSEL0

VSEL1

VSEL2

SELEN

CLK1

PWRDN

VCLK

MC

Figure 1

2

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