9LPRS525(2009) データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

9LPRS525
(Rev.:2009)

56-pin CK505 for Intel Systems

Integrated Device Technology 

ICS9LPRS525

PC MAIN CLOCK

Test Clarification Table

Comments

HW

SW

Power-up w/ TEST_SEL = 1 to enter test mode

Cycle power to disable test mode

FSLC./TEST_SEL -->3-level latched input

If power-up w/ V>2.0V then use TEST_SEL

If power-up w/ V<2.0V then use FSLC

FSLB/TEST_MODE -->low Vth input

TEST_MODE is a real time input

If TEST_SEL HW pin is 0 during power-up,

test mode can be invoked through B9b3.

If test mode is invoked by B9b3, only B9b4

is used to select HI-Z or REF/N

FSLB/TEST_Mode pin is not used.

Cycle power to disable test mode, one shot control

FSLC/

TEST_SEL

HW PIN

<2.0V

>2.0V

>2.0V

>2.0V

FSLB/

TEST

TEST_MODE ENTRY BIT

HW PIN

B9b3

X

0

0

X

0

X

1

X

REF/N or

HI-Z

B9b4

0

0

1

0

OUTPUT

NORMAL

HI-Z

REF/N

REF/N

>2.0V

1

X

1

REF/N

<2.0V

X

1

0

HI-Z

<2.0V

X

1

1

REF/N

B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B9b4: 1= REF/N, Default = 0 (HI-Z)

IDTTM/ICSTM PC MAIN CLOCK

18

1484A—04/28/09

Share Link: