9LPRS525 データシートの表示（PDF） - Integrated Device Technology

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9LPRS525

56-pin CK505 for Intel Systems

Integrated Device Technology 

ICS9LPRS525

PC MAIN CLOCK

General SMBus serial interface information for the ICS9LPRS525

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will acknowledge

• Controller (host) sends the beginning byte location = N

• ICS clock will acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• ICS clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• ICS clock sends Byte 0 through byte X (if X(H)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host)

ICS (Slave/Receiver)

T

starT bit

Slave Address D2(H)

WR

WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

ACK

Byte N + X - 1

P

stoP bit

ACK

IDTTM PC MAIN CLOCK

Index Block Read Operation

Controller (Host)

ICS (Slave/Receiver)

T

starT bit

Slave Address D2(H)

WR

WRite

ACK

Beginning Byte = N

ACK

RT

Repeat starT

Slave Address D3(H)

RD

ReaD

ACK

ACK

ACK

Data Byte Count = X

Beginning Byte N

N

Not acknowledge

P

stoP bit

Byte N + X - 1

1484B—01/21/10

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