A6850 データシートの表示（PDF） - Altera Corporation

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A6850

Asynchronous Communications Interface Adapter

Altera Corporation 

a6850 Asynchronous Communications Interface Adapter Data Sheet

The a6850 receives data with one or two stop bits. If one stop bit is

specified in the control register, the a6850 will expect one stop bit before

starting the synchronization process. Similarly, if two stop bits are

specified, the synchronization process begins after detecting two stop bits.

Error Detection

Three errors can occur when receiving: framing, overrun, and parity.

Refer to the status register error definitions on page 88 of this data sheet

for more information.

Receive Data Register Transfer

Once the last stop bit is received or a framing error is detected, the data in

the input shift register is transferred to the receiver data register. At this

point, all status bits associated with this data word are set, including the

rdrf bit. If receive interrupt is enabled, an interrupt on nirq is generated.

The receive process concludes when the microprocessor reads data from

the receiver data register.

Transmit Operation

The transmit operation includes the following functions:

s Transmit data register write/transfer

s Transmit start bit

s Transmit data

s Transmit parity bit

s Transmit stop bit

Transmit Data Register Write/Transfer

A transmit operation starts when the microprocessor writes data to the

transmitter data register. In the initial write operation, if the output shift

register is empty, data is immediately transferred and the shift operation

begins. However, if a shift operation is underway, the data is held in the

transmitter data register until the active shift operation is finished.

When data is in the transmitter data register, the tdre signal is cleared.

Once the data is transferred to the output shift register, the tdre status bit

is set. At this point, if transmit interrupt is enabled, an interrupt on nirq

is generated.

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Altera Corporation

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