A88
Line 11 10 9 8 7 6 5 4 3 2 1 0
Register Address / Bit
1
000000000000
2
000000000000
3
000011110000
4
000011110000
5
000001100000
6
000001100000
7
000001100000
8
000001100000
9
000001100000
10
000001100000
11
000001100000
12
000001100000
13
000001100000
14
000001100000
15
000011110000
16
000011110000
17
000000000000
18
000000000000
0x0a00 / BIT[11:0]
0x0a01 / BIT[11:0]
0x0a02 / BIT[11:0]
0x0a03 / BIT[11:0]
0x0a04 / BIT[11:0]
0x0a05 / BIT[11:0]
0x0a06 / BIT[11:0]
0x0a07 / BIT[11:0]
0x0a08 / BIT[11:0]
0x0a09 / BIT[11:0]
0x0a0a / BIT[11:0]
0x0a0b / BIT[11:0]
0x0a0c / BIT[11:0]
0x0a0d / BIT[11:0]
0x0a0e / BIT[11:0]
0x0a0f / BIT[11:0]
0x0a10 / BIT[11:0]
0x0a11 / BIT[11:0]
The above example depicts the Memory Font one 0xa00 ~ 0xa11. Similarly, one of the characters can
be represented in 0x812 ~ 0x823. In this way, you can store up to the end of the Font area.
K. Encoder block
Encoder block can be expressed as the following diagram.
SSG Block
1. Starting from Sync bus, if EVD/EHD/EPD input is received, Encoder relevant registers can specify
the value of the counter based on internal COUNTER generated BLOCK.
Timing Generation Block
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