AD73422BB-40 データシートの表示（PDF） - Analog Devices

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AD73422BB-40

Dual Low Power CMOS Analog Front End with DSP Microcomputer

Analog Devices 

AD73422–SPECIFICATIONS (AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, fDMCLK = 16.384 MHz,

fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)

Parameter

Min Typ Max Units Test Conditions

AFE SECTION

REFERENCE

REFCAP

Absolute Voltage, VREFCAP

REFCAP TC

REFOUT

Typical Output Impedance

Absolute Voltage, VREFOUT

Minimum Load Resistance

Maximum Load Capacitance

1.125 1.25

50

130

1.08 1.2

1

1.375

1.32

100

V

ppm/°C

Ω

V

kΩ

pF

0.1 µF Capacitor Required from

REFCAP to AGND2

Unloaded

INPUT AMPLIFIER

Offset

Maximum Output Swing

Feedback Resistance

Feedback Capacitance

± 1.0

1.578

50

100

mV

V

Max Output Swing = (1.578/1.25) ×

VREFCAP

kΩ

fC = 32 kHz

pF

ANALOG GAIN TAP

Gain at Maximum Setting

Gain at Minimum Setting

Gain Resolution

Gain Accuracy

Settling Time

Delay

+1

–1

5

Bits

Gain Step Size = 0.0625

± 1.0

%

Output Unloaded

1.0

ms

Tap Gain Change of –FS to +FS

0.5

ms

ADC SPECIFICATIONS

Maximum Input Range at VIN2, 3

Nominal Reference Level at VIN

(0 dBm0)

Absolute Gain

PGA = 0 dB

PGA = 38 dB

Gain Tracking Error

Signal to (Noise + Distortion)

PGA = 0 dB

PGA = 38 dB

Total Harmonic Distortion

PGA = 0 dB

PGA = 38 dB

Intermodulation Distortion

Idle Channel Noise

Crosstalk, ADC-to-DAC

ADC-to-ADC

DC Offset

Power Supply Rejection

Group Delay4, 5

Input Resistance at PGA2, 4, 6

1.578

–2.85

1.0954

–6.02

–0.5 0.4

+1.2

–0.7

± 0.1

72 78

78

55 57

56

–84 –73

–70

–65

–71

–100

–100

–70

–30 +10 +45

–65

25

20

V p-p

dBm

V p-p

dBm

dB

dB

dB

dB

dB

dB

dB

dB

dB

dB

dBm0

dB

dB

dB

mV

dB

µs

kΩ

Measured Differentially.

Max Input = (1.578/1.25) × VREFCAP

Measured Differentially

1.0 kHz, 0 dBm0

1.0 kHz, 0 dBm0

1.0 kHz, +3 dBm0 to –50 dBm0

300 Hz to 3400 Hz; fSAMP = 64 kHz

300 Hz to 3400 Hz; fSAMP = 8 kHz

0 Hz to fSAMP/2; fSAMP = 64 kHz

300 Hz to 3400 Hz; fSAMP = 64 kHz

300 Hz to 3400 Hz; fSAMP = 64 kHz

300 Hz to 3400 Hz; fSAMP = 64 kHz

PGA = 0 dB

PGA = 0 dB

ADC Input Level: 1.0 kHz, 0 dBm0

DAC Input at Idle

ADC1 Input Level: 1.0 kHz, 0 dBm0

ADC2 Input at Idle. Input Amps Bypassed

Input Amplifiers Included in Input

Channel

PGA = 0 dB

Input Signal Level at AVDD and DVDD

Pins: 1.0 kHz, 100 mV p-p Sine Wave

DMCLK = 16.384 MHz; Input

Amplifiers Bypassed and AGT Off

DIGITAL GAIN TAP

Gain at Maximum Setting

Gain at Minimum Setting

Gain Resolution

Delay

Settling Time

+1

–1

16

Bits

Tested to 5 MSBs of Settings

25

ms

Includes DAC Delay

100

ms

Tap Gain Change from –FS to +FS;

Includes DAC Settling Time

–2–

REV. 0

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