APA3160 データシートの表示（PDF） - Anpec Electronics

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APA3160

20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC

Anpec Electronics 

APA3160

Function Description (Cont.)

Single- and Multiple-Byte Transfers

The serial control interface supports single-byte and multiple-byte (R/W) operations for sub-addresses 0x00 to 0x1F.

However, for the sub-addresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write

operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the sub-address

assigned, as long as the master device continues to respond with acknowledges. If a particular sub-address does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that

are required for each specific sub-address.

Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APA3160

also supports sequential I2C addressing. For write transactions, if a sub-address is issued and followed by data for

that sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the

data for all 16 sub-addresses is successfully received by the APA3160. For I2C sequential write transactions, the sub-

address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is

transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential

addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last sub-

address, the data for the last sub-address is discarded. However, if all other data written is accepted, only the

incomplete data is discarded.

Single-Byte Write

As shown in Figure 11, a single-byte data write transfer begins with the master device transmitting a start condition

followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer. For a write

data transfer, the R/W bit will be a 0. After receiving the correct I2C device address and the R/W bit, the DAP responds

with an acknowledge bit. And then, the master transmits the address byte or bytes corresponding to the APA3160

internal memory address being accessed. After receiving the address byte, the APA3160 responds with an acknowl-

edge bit again. Next, the master device transmits the data byte to be written to the memory address being accessed.

After receiving the data byte, the APA3160 again responds with an acknowledge bit. Finally, the master device trans-

mits a stop condition to complete the single-byte data write transfer.

Start

Condition

Acknowledge

Acknowledge

Acknowledge

A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I2C Device Address

and Read/ Write Bit

Sub-address

Data Byte

Stop

Condition

Figure 11. Single-Byte Write Transfer

Copyright © ANPEC Electronics Corp.

16

Rev. A.4 - Jan., 2013

www.anpec.com.tw

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