ATT3042 データシートの表示（PDF） - Unspecified

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ATT3042

Field-Programmable Gate Arrays

Unspecified 

ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Configuration Modes (continued)

Peripheral Mode

Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor

peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the com-

mon assertion of the active-low write strobe (WS), and two active-low and one active-high chip selects (CS0, CS1,

CS2). If all of these signals are not available, the unused inputs should be driven to their respective active levels.

The FPGA will accept 1 byte of configuration data on the D[7:0] inputs for each selected processor write cycle.

Each byte of data is loaded into a buffer register. The FPGA generates a CCLK from the internal timing generator

and serializes the parallel input data for internal framing or for succeeding slaves on data out (DOUT). An output

HIGH on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a

new byte. As with master modes, peripheral mode may also be used as a lead device for a daisy-chain of slave

devices.

CONTROL ADDRESS

SIGNALS BUS

DATA

BUS

8

M0 M1

PWRDWN

+5 V

5 kΩ

D[7:0]

D[7:0]

CCLK

*

+5 V

ADDRESS

DECODE

LOGIC

REPROGRAM

OC

CS0

CS1

CS2

WS

RDY/BUSY

INIT

D/P

RESET

DOUT

M2

HDC

LDC

OTHER

I/O PINS

Figure 23. Peripheral Mode

*

GENERAL-

PURPOSE

USER I/O

5-3114(F)

24

Lucent Technologies Inc.

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