C0240QGLA-T データシートの表示（PDF） - AZ Displays

部品番号

コンポーネント説明

メーカー

C0240QGLA-T

Approval Product Specification

AZ Displays 

34

DB6

35

DB5

36

DB4

37

DB3

38

DB2

39

DB1

40

DB0

41 VSYNC

42 HSYNC

43 DOTCLK

44 ENABLE

45

SDI

(SDIN)

46

SDO

(SDOUT)

47

CSB

(CS/NCS)

48 RW_WRB

(SCL)

49

RS

50 E_RDB

Document No.:

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Frame-synchronizing signal.

I (VSPL=0 Low active, VSPL=1 High active)

FIX this pin at VSS level if the pin is not used

Line-synchronizing signal.

I (HSPL=0 Low active, HSPL=1 High active)

FIX this pin at VSS level if the pin is not used

Input pin for clock signal of external interface : dot clock.

I

DPL=0 Display data is fetched at DOTCLK’s rising edge

DPL=1 Display data is fetched at DOTCLK’s falling edge

Fix this pin at VSS level if the pin is not used.

Data enablesignal pin for RGB interface.

EPL

ENABLE GRAM write

GRAM

address

I

0

0

Valid

Updated

0

1

Invalid

Held

1

0

Invalid

Held

1

1

Valid

Updated

For a serial peripheral interface (SPI), input data is fetched at

I the rising edge of the SCL signal, Fix SDI pin at VSS level if the

pin is not used.

For a serial peripheral interface (SPI), serves as the serial data

O output pin (SDO), Successive bits are output at the falling edge

of the SCL signal.

Chip select signal input pin.

I 0= driver IC is selected and can be accessed.

1= driver IC is not selected and cannot be accessed.

Pin function

CPU type

Pin description

Read/Write operation

RW

68-system selection pin

I

0=write 1=read

Write strobe signal.(Input pin)

WRB

80_system Data is fetched at the rising

edge.

SCL

SPI

The synchronous clock signal

Register select pin.

I 0=Index/status, 1=instruction parameter, GRAM data

Must be fixed at VDD3 level when not used.

Pin Function CPU type

Pin description

E

I

RDB

68-system

80_system

Read/Writeoperation enable

pin

Read strobe signal.

Read out data at the low level

When SPI mode is selected, fix this pin at VDD3 levle

18

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