CXA3010 データシートの表示（PDF） - Sony Semiconductor

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CXA3010

Read/Write Amplifier (with Built-in Filters) for FDDs

Sony Semiconductor 

CXA3010Q

Erase Current Setting Method

The erase circuit in this IC generates the erase current by using a constant current circuit; the current value is

determined according to the following formula, based on the resistor RE connected to Pin 28.

IE = 11.8/RE [mA] RE: [kΩ]

Erase Current Rise and Fall Times (Refer to Fig. 3)

In this IC, time constants are provided for the erase current rise and fall in order to prevent bad writes due to

write head crosstalk.

The current rise and fall times of the constant current circuit in the IC is 1.3µs, but the potential difference VA

that develops in the head when the erase current is turned on and off is as shown below. Because the circuit

clamp is generated according to this VA value, the rise and fall times differ. Therefore, refer to the explanation

provided below when using this IC.

VA = L × di (L: head inductance; di: erase current; dt: 1.3µs)

dt

1. When erase current turns on

(1) When the potential difference VA in the head is (VCC – 1.8V) or more

When the current turns on, potential difference VA is generated in the head; if VA is equal to (VCC –1.8V) or

more, the erase output transistor Q1 shown in the circuit in Fig. 3 becomes saturated, and the pin voltage is

clamped at approximately 1.8V. Voltage driving results, and the rise time Tr is as follows:

Tr =

L × IE

VCC – 1.8

×

1

1000

[µs]

L: [µH], IE: [mA], VCC: [V]

(2) When the potential difference VA in the head is (VCC – 1.8V) or less

In this case, because VA does not reach clamping level, the rise time becomes the rise time of IE in the

circuits within the IC.

Current rise time Tr = 1.3µs

– 20 –

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