EL1056 データシートの表示（PDF） - Intersil

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EL1056

Monolithic High-Speed Pin Driver

Intersil 

EL1056A, EL1056

Overcurrent Protection

The sense comparators are available to alert the test

system's controller that the driver is outputting excessive

current. Shunt resistors are connected from B+ to Shunt+

and B- to Shunt-. When the internal comparators sense

more than a nominal 200mV drop on the shunts, they cause

a 1.5mA current to be sunk from the Sense terminal. The

comparators are of “slow attack, fast decay” design, so that

transient load currents will not trigger a sense output; only a

sustained over-current will.

The sense resistors must not be inductive, and the skin

resistance of long, narrow connections between Shunt and

B+ or B- can cause transient voltages that produce output

overshoot (but not ringing).

The Sense output is simply a switched current source

connected to V-. It can be used to interface to CMOS, TTL,

or ECL inputs. For CMOS and TTL, it can be connected to a

pull-up resistor to +5V of 10K value. This establishes a logic

high value, and a clamp diode (internal to TTL) establishes a

low level of -0.6V. For ECL, a gate should be available to

provide a static logic high level. An 820Ω pull-up resistor is

wired to that output. The logic low will be more negative than

is usual for ECL, but this will cause no problem. In all cases,

multiple Sense outputs may be connected together from

many drivers to effect a wired-or function.

A further protection scheme is to provide a series resistor

from B+ to V+ and B- to V-. The resistor serves to limit the

output fault current by allowing B+ and B- voltages to sag

under heavy load. This also reduces the dissipation on the

output transistors for valid loads. Because B+ and B- are

separately bypassed, these voltages will sustain under

transient loads and dynamics will not be affected.

Output Accuracy

The accuracy of the output voltage depends on several

factors. The first is the gain error from VINH or VINL to the

output, unloaded. The gain error is nominally -0.6%, and has

a few tenths of a percent variation between parts. The

second is supply rejection. If the B+, B-, Shunt+, or Shunt-

voltages are different from those used by Elantec to test the

part, there will be about 2.2mV systematic shift in output

offset per volt of supply variation. The V+ and V- supplies

have much less influence on output error. Finally, there is a

random VOS error as specified in the data table.

Of course, the finite output impedance of the EL1056 will

cause additional output error when the driver is loaded.

Power-Down

The EL1056 incorporates a power-down feature that

drastically reduces power consumption of an unused driver

and also drops the output leakage current to nanoamperes

(“A” grade only). The output is not a low capacitance in this

mode, however, and transients driven from the cable can

momentarily turn on the output transistors. Power-down is

intended to allow the switching of accurate DC meters onto

the bus without having to relay out the driver's leakage

current. It takes about 40µs for the output leakage to sag to

nanoamperes, but this is still much faster than relays or

voltmeters.

Power-down is controlled by the E and E differential inputs.

There is no problem with logic amplitude or slewrate, and

input resistor networks are not needed.

Supply and Input Bypassing

The V+, B+, V-, and B- leads should be bypassed very

closely with 0.1µF capacitors, preferably chip type. There

should be a wide ground plane between bypasses, and this

can be the heatsink copper. It is wise to also have a 4.7µF

tantalum bypass capacitor within a couple of inches to the

driver.

The logic inputs are active device bases, and can oscillate if

presented with inductive lines. A local resistor of 1000Ω or

less to ground will suffice in de-Q'ing any resonance. A

100pF or larger capacitor can also serve as a bypass.

Thermal Considerations

The package of the EL1056 includes two fused leads on

each side which are connected to the internal die mounting

metal. Heat generated in the die flows through the mounting

pad to the fused leads, and then to the circuit-board copper,

achieving a thermal resistance to air around 40°/W.

Characterization curves show the thermal resistance versus

airflow rate. Consult the EL1056 Demonstration Board

literature for a suggested board pattern. Note that thicker

layers of copper than we used improves the thermal

resistance further, to a limit of 22°C/W for an “infinite

heatsink” directly soldered to the fused leads.

As a practical limit, the die temperature should be kept to

125°C rather than the allowable 150°C to retain optimum

timing accuracies.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

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