SST89E554 データシートの表示（PDF） - Silicon Storage Technology

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SST89E554

Flash flex 51 MCU

Silicon Storage Technology 

SPI Status Register (SPSR)

Location

AAH

7

SPIF

6

WCOL

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

5

4

3

2

1

0

Reset Value

-

-

-

-

-

-

00xxxxxxb

Symbol

SPIF

WCOL

Function

Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is

then generated. To clear, read SPSR and then access SPDR.

Set if the SPI data register is written to during data transfer. To clear, read SPSR and

then access SPDR.

SPI Data Register (SPDR)

Location

86H

7

SPD7

6

SPD6

5

SPD5

4

SPD4

3

SPD3

2

SPD2

1

SPD1

0

Reset Value

SPD0

00H

Power Control Register (PCON)

Location

7

6

5

4

3

2

1

87H SMOD1 SMOD0 BOF

POF

GF1

GF0

PD

0

Reset Value

IDL 00010000b

Symbol

SMOD1

SMOD0

BOF

POF

GF1

GF0

PD

IDL

Function

Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate.

FE/SM0 Selection bit.

0: SCON[7] = SM0

1: SCON[7] = FE,

Brown-out detection status bit, this bit will not be affected by any other reset. BOF should

be cleared by software. Power-on reset will also clear the BOF bit.

0: No Brown-out.

1: Brown-out occurred

Power-on reset status bit, this bit will not be affected by any other reset. POF should be

cleared by software.

0: No Power-on reset.

1: Power-on reset occurred

General-purpose flag bit.

General-purpose flag bit.

Power-down bit.

0: Power-down mode is not activated.

1: Activates Power-down mode.

Idle mode bit.

0: Idle mode is not activated.

1: Activates Idle mode.

©2001 Silicon Storage Technology, Inc.

22

S71181-03-000 9/01 384

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