TDA7580(2002) データシートの表示（PDF） - STMicroelectronics

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TDA7580
(Rev.:2002)

FM/AM digital IF sampling processor

STMicroelectronics 

TDA7580

INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA DIVERSITY

Figure 10. High Speed Synchronous Serial Interface - HS3I

Master Bit Clock

Master Data Out

Master Synch

Slave Data Out

M2 M3

256 cycles of 74.1MHz

S0 S1 S2 S3

Master Bit Clock

Master Data Out

Master Synch

Slave Data Out

tmbco

tmbcs

tmbcc

tsdos

Timing

TDSP

tmbcc

tmbco

tmbcs

tsdos

Description

Internal DSP Clock Period (Typical 1/74.1MHz)

MBC minimum Clock Cycle

MBC active edge to master data out valid

MBC active edge to master synch valid

Slave Data Out setup time

Note TDSP = DSP master clock cycle time = 1/FDSP

20/31

Value

32*TDSP

4

4

6

Unit

ns

ns

ns

ns

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