PM7382 データシートの表示（PDF） - PMC-Sierra

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PM7382

FRAME ENGINE AND DATALINK MANAGER 32P256

PMC-Sierra 

RELEASED

DATA SHEET

PMC-2010333

ISSUE 3

PM7382 FREEDM-32P256

FRAME ENGINE AND DATA LINK MANAGER 32P256

supports the validation of both CRC-CCITT and CRC-32 frame check

sequences.

· For each channel, the receiver checks for packet abort sequences, octet

aligned packet length and for minimum and maximum packet length. The

receiver supports filtering of packets that are larger than a user specified

maximum value.

· Alternatively, for each channel, the receiver supports a transparent mode

where each octet is transferred transparently to host memory. For

channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64

kbits/s clear channel format.

· For each channel, the HDLC transmitter supports programmable flag

sequence generation, bit stuffing and frame check sequence generation. The

transmitter supports the generation of both CRC-CCITT and CRC-32 frame

check sequences. The transmitter also aborts packets under the direction of

the host or automatically when the channel underflows.

· Supports two levels of non-preemptive packet priority on each transmit

channel. Low priority packets will not begin transmission until all high priority

packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode

where each octet is inserted transparently from host memory. For

channelised links, the octets are aligned with the transmit time-slots.

· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the

transmit and receive directions. This memory may be configured to support a

variety of different channel configurations from a single channel with 32

Kbytes of buffering to 256 channels, each with a minimum of 48 bytes of

buffering.

· Supports PCI burst sizes of up to 256 bytes for transfers of packet data.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 Volt PCI signaling environments.

· Supports 5 Volt tolerant I/O (except PCI).

· Low power 2.5 Volt 0.25 mm CMOS technology.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 2

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