PM7382-PI データシートの表示（PDF） - PMC-Sierra

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PM7382-PI

FRAME ENGINE AND DATALINK MANAGER 32P256

PMC-Sierra 

RELEASED

DATA SHEET

PMC-2010333

ISSUE 3

PM7382 FREEDM-32P256

FRAME ENGINE AND DATA LINK MANAGER 32P256

optionally separated by two flags (an opening flag and a closing flag) or a single

flag (combined opening and closing flag). Zeros between flags are not shared.

PCI bus latency may cause one or more channels to underflow, in which case,

the packets are aborted, and the host is notified. For normal traffic, an abort

sequence is generated, followed by inter-frame time fill characters (flags or all-

ones bytes) until a new packet is sourced from the PCI host. No attempt is made

to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-32P256 supports a

transparent operating mode. For each provisioned transparent channel, the

FREEDM-32P256 directly inserts the transmitted octets from host memory. If the

transparent channel is assigned to a channelised link, then the octets are aligned

to the transmitted time-slots. If a channel underflows due to excessive PCI bus

latency, an abort sequence is generated, followed by inter-frame time fill

characters (flags or all-ones bytes) to indicate idle channel. Data resumes

immediately when the FREEDM-32P256 receives new data from the host.

The FREEDM-32P256 is configured, controlled and monitored using the PCI bus

interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P256 is

implemented in low power 2.5 Volt 0.25 mm CMOS technology. All non-PCI

FREEDM-32P256 I/O pins are 5 volt tolerant. The FREEDM-32P256 is

packaged in a 329 pin plastic ball grid array (PBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9

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