H5PS2562GFR データシートの表示（PDF） - Hynix Semiconductor

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H5PS2562GFR

256Mb DDR2 SDRAM

Hynix Semiconductor 

H5PS2562GFR series

IDD Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)

Symbol

Conditions

IDD0

Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS =

tRAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are

SWITCHING;Data bus inputs are SWITCHING

Units

mA

IDD1

Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL

= 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH,

CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same

mA

as IDD4W

IDD2P

Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING

mA

IDD2Q

Precharge quiet standby current ; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

mA

IDD2N

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other

control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

Active power-down current; All banks open; tCK = tCK(IDD); Fast PDN Exit MRS(12) = 0

mA

IDD3P CKE is LOW; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Slow PDN Exit MRS(12) = 1

mA

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

IDD3N =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus

mA

inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),

IDD4W AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH

mA

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,

IDD4R

CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS

is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as

mA

IDD4W

Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is

IDD5B HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-

mA

ING; Data bus inputs are SWITCHING

IDD6

Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

mA

Rev.1.3 / June. 2012

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