L6590 データシートの表示（PDF） - STMicroelectronics

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L6590

FULLY INTEGRATED POWER SUPPLY

STMicroelectronics 

L6590

APPLICATION INFORMATION

In the following sections the functional blocks as well as the most important internal functions of the device will

be described.

Start-up Circuit

When power is first applied to the circuit and the voltage on the bulk capacitor is sufficiently high, an internal

high-voltage current generator is sufficiently biased to start operating and drawing about 4.5 mA through the

primary winding of the transformer and the drain pin. Most of this current charges the bypass capacitor connect-

ed between pin Vcc (3) and ground and makes its voltage rise linearly.

As the Vcc voltage reaches the start-up threshold (14.5V typ.) the chip, after resetting all its internal logic, starts

operating, the internal power MOSFET is enabled to switch and the internal high-voltage generator is discon-

nected. The IC is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an

auxiliary winding of the transformer) develops a voltage high enough to sustain the operation.

As the IC is running, the supply voltage, typically generated by a self-supply winding, can range between 16 V

(Overvoltage protection limit, see the relevant section) and 7 V, threshold of the Undervoltage Lockout. Below

this value the device is switched off (and the internal start-up generator is activated). The two thresholds are in

tracking.

The voltage on the Vcc pin is limited at safe values by a clamp circuit. Its 17V threshold tracks the Overvoltage

protection threshold.

Figure 32. Start-up circuit internal schematic

DRAIN

15 MΩ

UVLO

Vcc

150 Ω

17 V

POWER

MOSFET

GND

Power MOSFET and Gate Driver

The power switch is implemented with a lateral N-channel MOSFET having a V(BR)DSS of 700V min. and a typ-

ical RDS(on) of 13Ω. It has a SenseFET structure to allow a virtually lossless current sensing (used only for pro-

tection).

During operation in Discontinuous Conduction Mode at low mains the drain voltage is likely to go below ground.

Any risk of injecting the substrate of the IC is prevented by an internal structure surrounding the switch.

The gate driver of the power MOSFET is designed to supply a controlled gate current during both turn-on and

turn-off in order to minimize common mode EMI.

Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power MOS-

FET cannot be turned on accidentally.

14/23

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