M12L128168A-5TIG データシートの表示（PDF） - [Elite Semiconductor Memory Technology Inc.

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M12L128168A-5TIG

2M x 16 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L128168A

Operation temperature condition -40°C ~85°C

Write command

( CS , CAS , WE = Low, RAS = High)

If the mode register is in the burst write mode, this command sets the burst start

address given by the column address to begin the burst write operation. The first

write data in burst can be input with this command with subsequent data on following

clocks.

CLK

CKE

H

CS

RAS

CAS

WE

A12, A13

(Bank select)

A10

Add

Col.

Fig. 4 Column address and

write command

Read command

( CS , CAS = Low, RAS , WE = High)

Read data is available after CAS latency requirements have been met.

This command sets the burst start address given by the column address.

CLK

CKE

CS

RAS

CAS

WE

A12, A13

(Bank select)

A10

Add

H

Col.

Fig. 5 Column address and

read command

CBR (auto) refresh command

( CS , RAS , CAS = Low, WE , CKE = High)

This command is a request to begin the CBR refresh operation. The refresh

address is generated internally.

Before executing CBR refresh, all banks must be precharged.

After this cycle, all banks will be in the idle (precharged) state and ready for a

row activate command.

During tRC period (from refresh command to refresh or activate command), the

M12L128168A cannot accept any other command.

CLK

CKE

H

CS

RAS

CAS

WE

A12, A13

(Bank select)

A10

Add

Fig. 6 Auto refresh command

Elite Semiconductor Memory Technology Inc.

Publication Date: Oct. 2007

Revision: 1.2

14/43

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