M12L16161A-7BIG データシートの表示（PDF） - [Elite Semiconductor Memory Technology Inc.

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M12L16161A-7BIG

512K x 16Bit x 2Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L16161A

Operation temperature condition -40℃~85℃

Page Read Cycle at Different Bank @ Burst Length=4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

15 16

17 18

19

CLOCK

CKE

*Note1

CS

HIGH

RAS

CAS

*Note2

ADDR

RAa

CAa RBb

CBb

BA

CAc

CBd

CAe

A10/AP

RAa

RBb

CL=2

DQ

CL=3

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

WE

DQM

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.

2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 1.1

16/29

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