M32171F3VFP データシートの表示（PDF） - Mitsumi

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M32171F3VFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

Mitsumi 

2001-5-14 Rev.1.0

Mitsubishi Microcomputers

32171 Group

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

Built-in 10-Channel DMAC

The microcomputer contains 10 channels of DMAC, allowing

for data transfer between internal peripheral I/Os, between

internal RAM and internal peripheral I/O, and between inter-

nal RAMs.

DMA transfer requests can be issued from the user-cre

ated software, as well as can be triggered by a signal gener-

ated by the internal peripheral I/O (A-D converter, MJT, or

serial I/O).

The microcomputer also supports cascaded connection be-

tween DMA channels (starting DMA transfer on a channel at

end of transfer on another channel). This makes advanced

transfer processing possible without causing any additional

CPU load.

Table 11 Outline of the DMAC

Item

Number of channels

Content

10 channels

Transfer request

Maximum number of times transferred

Transferable address space

Transfer data size

Transfer method

• Software trigger

• Request from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O

(reception completed, transmit buffer empty)

• Cascaded connection between DMA channels possible (Note)

256 times

• 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF)

• Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO,

and between internal RAMs are supported

16 bits or 8 bits

Single transfer DMA (control of the internal bus is relinquished for each transfer performed),

dual-address transfer

Transfer mode

Single transfer mode

Direction of transfer

Channel priority

Maximum transfer rate

Interrupt request

Transfer area

One of three modes can be selected for the source and destination of transfer:

• Address fixed

• Address increment

• 32-channel ring buffer

Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 >

channel 5 > channel 6 > channel 7 > channel 8 > channel 9

(Fixed priority)

13.3 Mbytes per second (when internal peripheral clock = 20 MHz)

Group interrupt request can be generated when each transfer count register underflows

64 Kbytes from H’0080 0000 to H’0080 FFFF (Transfer is possible in the entire internal

RAM/SFR area)

Note: The following DMA channels can be cascaded.

DMA transfer on channel 1 started at end of one DMA transfer on channel 0

DMA transfer on channel 2 started at end of one DMA transfer on channel 1

DMA transfer on channel 0 started at end of one DMA transfer on channel 2

DMA transfer on channel 4 started at end of one DMA transfer on channel 3

DMA transfer on channel 6 started at end of one DMA transfer on channel 5

DMA transfer on channel 7 started at end of one DMA transfer on channel 6

DMA transfer on channel 5 started at end of one DMA transfer on channel 7

DMA transfer on channel 9 started at end of one DMA transfer on channel 8

DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register)

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