MACH210-12JC データシートの表示（PDF） - Lattice Semiconductor
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MACH210-12JC Datasheet PDF : 47 Pages
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)
Parameter
Symbol
tIGS
Parameter Description
Input Latch Gate to Output Latch Setup
-7
Min
Max Unit
10
ns
tWIGL
Input Latch Gate Width LOW
3
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
11.5
ns
tAR
Asynchronous Reset to Registered or Latched Output
12
ns
tARW
Asynchronous Reset Width
8
ns
tARR
Asynchronous Reset Recovery Time
8
ns
tAP
Asynchronous Preset to Registered or Latched Output
12
ns
tAPW
Asynchronous Preset Width
8
ns
tAPR
Asynchronous Preset Recovery Time
8
ns
tEA
Input, I/O, or Feedback to Output Enable
7.5
ns
tER
Input, I/O, or Feedback to Output Disable
7.5
ns
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
12
MACH210A-7 (Com’l)
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