NT5SV16M4DT データシートの表示（PDF） - Unspecified

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NT5SV16M4DT

64Mb Synchronous DRAM

Unspecified 

NT5SV16M4DT

NT5SV8M8DT

NT5SV4M16DT

64Mb Synchronous DRAM

AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)

1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must

be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between VIH and VIL (or between VIL and VIH)

3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL

and VIH) in a monotonic manner.

4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point

5. Load Circuit A: AC measurements assume tT = 1.0ns.

6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point

7. Load Circuit B: AC measurements assume tT = 1.2ns.

.

AC Characteristics Diagrams

Clock

Input

Output

tCKL

tSETUP

tHOLD

1.4V

tAC

tLZ

tCKH

tT

VIH

1.4V

VIL

tOH

1.4V

Output

Zo = 50Ω

AC Output Load Circuit (A)

Vtt = 1.4V

50Ω

50pF

Output

Zo = 50Ω

AC Output Load Circuit (B)

50pF

REV 1.1

10/01

16

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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