PCF8598C-2P データシートの表示（PDF） - Integrated Circuit Systems
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PCF8598C-2P Datasheet PDF : 24 Pages
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Philips Semiconductors
256 to 1024 × 8-bit CMOS EEPROMs with
I2C-bus interface
Product specification
PCF85xxC-2 family
SYMBOL
PARAMETER
SDA input/output (pin 5)
VIL
LOW level input voltage
VIH
HIGH level input voltage
VOL
LOW level output voltage
ILO
output leakage current
CI
input capacitance
Data retention time
tS
data retention time
CONDITIONS
IOL = 3 mA; VDD(min)
VOH = VDD
VI = VSS
Tamb = 55 °C
MIN.
MAX.
UNIT
−0.8
0.3VDD V
0.7VDD +6.5
V
−
0.4
V
−
1
µA
−
7
pF
10
−
years
11 I2C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and
VIH with an input voltage swing from VSS to VDD; see Fig.10.
SYMBOL
PARAMETER
fSCL
clock frequency
tBUF
bus free time between a STOP and START
condition
tHD;STA
START condition hold time after which first clock
pulse is generated
tLOW
tHIGH
tSU;STA
tHD;DAT
LOW level clock period
HIGH level clock period
set-up time for STARt condition
data hold time
for bus compatible masters
for bus devices
tSU;DAT
tr
tf
tSU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
CONDITIONS
MIN.
0
4.7
MAX.
100
−
UNIT
kHz
µs
4.0
−
µs
4.7
−
µs
4.0
−
µs
repeated start 4.7
−
µs
note 1
5
−
µs
0
−
ns
250
−
ns
−
1
µs
−
300
ns
4.0
−
µs
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
1997 Feb 13
12
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