NXP Semiconductors
PHD78NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
[1] It is not possible to make a connection to pin 2.
Simplified outline
mb
[1]
2
1
3
SOT428
(SC-63; DPAK)
3. Ordering information
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PHD78NQ03LT SC-63;
DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
Version
SOT428
PHD78NQ03LT_6
Product data sheet
Rev. 06 — 11 June 2009
© NXP B.V. 2009. All rights reserved.
2 of 12