SAA7710T データシートの表示（PDF） - Philips Electronics

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SAA7710T

Dolby* Pro Logic Surround; Incredible Sound

Philips Electronics 

Philips Semiconductors

Dolby* Pro Logic Surround;

Incredible Sound

Product specification

SAA7710T

I2C-BUS FUNCTION BITS

Input selector control register

The write only, two byte, input selector control register is

located on absolute address 0FFFH (4095) and consists

of 16 bits, starting with bit 0 and ending with bit 15.

Deviation from the I2C-bus specification

1. The data hold time (tHD;DAT) for this device (≥0 ns as

stated in the I2C-bus specification) should be as

follows:

a) For the crystal oscillator mode (SHTCB = 0):

≥





f--x--6-t--a--l

b) For the slave oscillator mode (SHTCB = 0):

≥





f--s---l-6a---v---e- 

c) For the slave oscillator mode (SHTCB = 1):

≥





f--s---l-3a---v---e- 

During the write cycle, the I2C-bus clock frequency must

be reduced.

The I2C-bus clock frequency has the following constraints:

fs > 2 × fIIC

fs = I2S-bus sampling frequency

fIIC = I2C-bus clock frequency.

If this constraint cannot be met, a higher I2C-bus frequency

can be obtained in the following way:

By making the I2C-bus master insert a delay (td) after the

acknowledge pulse (see Fig.11). The delay should be

larger than or equal to 1/fs where fs is the I2S-bus

sampling frequency.

By not using the auto-increment feature. This means

that each data word must be preceded by its intended

destination address.

handbook, full pagewidth

SCL

SDA

ACKNOWLEDGE AFTER WORD

auto-increment address register

td

MGE756

1998 Mar 13

Fig.11 Timing of reduced I2C-bus frequency.

13

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