tm TE
CH
T431616A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
H IG H
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb RAc
CAc
BA
A 10/A P
RAa
CL=2
DQ
CL=3
RBb
Q A a0 Q A a1 Q A a2 Q A a3
Q A a0 Q A a1 Q A a2 Q A a3
RAc
tC D L
*N ote1
DBb0 DBb1 DBb2 DBb3
Q A c0 Q A c1 Q A c2
DBb0 DBb1 DBb2 DBb3
Q A c0 Q A c1
WE
DQM
R o w A ctiv e
(A -B ank)
R ead (A -
B ank)
R o w A ctiv e
(B -B ank)
P recharge
(A -B ank)
W rite (B -
B ank)
R o w A ctiv e
(A -B ank)
R ead (A -
B ank)
:D o n 't c a re
*Note : 1. tCDL should be met to complete write.
Taiwan Memory Technology, Inc. reserves the right P.21
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C