Z80C3016VSG データシートの表示（PDF） - Zilog

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Z80C3016VSG

CMOS SCC Serial Communications Controller

Zilog 

CMOS SCC Serial Communications Controller

Product Specification

10

AD7–AD0

Address/Data Bus (bidirectional, active High, Tri-state) . These multiplexed lines

carry register addresses to the SCC as well as data or control information.

AS

Address Strobe (input, active Low) . Addresses on AD7–AD0 are latched by the rising

edge of this signal.

CS0

Chip Select 0 (input, active Low) . This signal is latched concurrently with the

addresses on AD7–AD0 and must be active for the intended bus transaction to occur.

CS1

Chip Select 1 (input, active High) . This second select signal must also be active before

the intended bus transaction can occur. CS1 must remain active throughout the transaction.

DS

Data strobe (input, active Low) . This signal provides timing for the transfer of data into

and out of the SCC. If AS and DS coincide, this confluence is interpreted as a reset.

R/W

Read/Write (input) . This signal specifies whether the operation to be performed is a

Read or a Write.

PS011706-0511

Pin Descriptions

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