Q67000-A9284-X201-K5 データシートの表示（PDF） - Infineon Technologies

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Q67000-A9284-X201-K5

High Performance Power Combi Controller

Infineon Technologies 

TDA 16888

The pulse-width-modulation of the PWM section is trailing edge modulated according to

the PWM ramp signal VPWM RMP at pin 15 (PWM RMP) and the input voltage VPWM IN at

pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulse-

width-modulation of the PWM section is trailing edge triggered with respect to the

internal clock reference CLK OUT in order to avoid undesirable electromagnetic

interference of both sections. Moreover the maximum duty cycle of the PWM is limited

to 50% to prevent transformer saturation.

By means of the above mentioned improved current mode control a stable pulse-width-

modulation from maximum load down to no load is achieved. Finally, in case of no load

conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to

ground.

Data Sheet

9

2000-02-28

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