MU9C8358L-THC データシートの表示（PDF） - MUSIC Semiconductors

部品番号

コンポーネント説明

メーカー

MU9C8358L-THC

Quad 10/100Mb Ethernet Filter Interface

MUSIC Semiconductors 

3LQ 'HV.ULSWLRQV

08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H

+RVW 3UR.HVVRU ,QWHUID.H

The Host Processor interface is asynchronous to the

System Clock. This interface is controlled by the /PCS or

/PCSS (whichever is appropriate) and PROC_RDY

signals, which form the handshaking between the

processor and the MU9C8358L. This allows the end

system to use a processor that runs at a different clock

speed than the clock required by the MU9C8358L. See

Timing Diagrams: Timing Data for Host Processor

Interface.

3&6 3UR.HVVRU 3RUW &KLS 6HOH.W ,QSXW 77/

Processor Chip Select is taken LOW by the host processor

to gain access to the MU9C8358L Port or Chip registers.

When two MU9C8358L devices are connected together,

each device should have its own independent /PCS signal.

3&66 3UR.HVVRU 3RUW &KLS 6HOH.W 6\VWHP

,QSXW 77/

Processor Chip Select System is taken LOW by the host

processor to gain access to the MU9C8358L System

registers or to access the LANCAM. When two

MU9C8358L devices are connected together, the /PCSS

inputs should be connected together.

:5,7( 3UR.HVVRU 3RUW 5HDG:ULWH ,QSXW 77/

Read/Write determines the direction of data flow into or

out of the MU9C8358L host processor interface. If

/WRITE is LOW, the data is written into the register

selected by A[7:0] and /PCS or /PCSS; if HIGH, the data

is read from the register selected by A[7:0] and /PCS or

/PCSS.

$>@ 3UR.HVVRU 3RUW $GGUHVV ,QSXW 77/

Processor Address bus A[7:0] selects the MU9C8358L

register accessed by the host processor.

'>@ 3UR.HVVRU 3RUW 'DWD ,QSXW2XWSXW

7ULVWDWH 77/

Processor Data bus D[15:0] is the tri-state processor data

bus for the MU9C8358L.

352&B5'< 3UR.HVVRU 3RUW 5HDG\ 2XWSXW

7ULVWDWH 77/

When reading from or writing to any MU9C8358L

internal register, the PROC_RDY tri-state output goes

LOW on the falling edge of /PCS or /PCSS. It goes HIGH

on the rising edge of the first SYSCLK after /PCS or

/PCSS is LOW, to indicate that data is available (read) or

data has been accepted (write).

,175 3UR.HVVRU ,QWHUUXSW 2XWSXW 77/

/INTR goes LOW to signal that one of the four

configurable interrupt conditions have been satisfied. The

four separate conditions are configured by setting bits in

the appropriate register. /INTR returns HIGH when the

appropriate register is read. See Table 2 for details of

which interrupt conditions are possible and which register

must be read to reset the /INTR pin to HIGH.

7DEOH  ,175 6HWWLQJV

5HJLVWHU 7R &OHDU

5HTXLUHG ,175 5HDG

WR 6HOH.W

,QWHUUXSW

&RQGLWLRQ

,QWHUUXSW &RQGLWLRQ

37$5*

567$7 5HIHU 2QH RI WKH 0,, SRUWV KDV SDUVHG DQ

WR 1RWHV EHORZ LQ.RPLQJ SD.NHW 7KH '$ ORRNXS KDV

EHHQ SHUIRUPHG DQG WKH UHVXOW GDWD

LV DYDLODEOH WR EH UHDG IURP WKH

5'$7 UHJLVWHU

67$5*

667$7 5HIHU 7KH )) RXWSXW IURP WKH /$1&$0 V

WR 1RWHV EHORZ KDV LQGL.DWHG WKDW WKH /$1&$0 LV

IXOO :KHQ UHDGLQJ WKH 667$7

UHJLVWHU D IXOO .RQGLWLRQ LV LQGL.DWHG

E\ ELW  

Notes:

1. RSTAT–/INTR only returns HIGH when all possible result data has

been read.

2. SSTAT–/INTR only returns HIGH when the LANCAM has become

not full. Therefore, after the SSTAT register read has confirmed the

status of the interrupt condition, an entry should be removed from

the LANCAM by using the PURGE sequence.

/$1&$0 ,QWHUID.H

See Timing Diagrams: Timing Data for LANCAM

Interface.

'4>@ /$1&$0 %XV ,QSXW2XWSXW 7ULVWDWH

77/

DQ[15:0] tri-state 16-bit bus transfers data or instructions

between the MU9C8358L and the LANCAM. When no

data or instructions are present on the bus, the bus goes

HIGH-Z. These pins have 50-kΩ internal pull-up resistors.

( /$1&$0 %XV (QDEOH 2XWSXW 7ULVWDWH 77/

The /E chip enable is taken LOW to initiate LANCAM

activity. On LANCAM read cycles, /E is taken HIGH after

the MU9C8358L registers the data. This pin has a 50-kΩ

internal pull-up resistor.

: /$1&$0 %XV :ULWH 2XWSXW 7ULVWDWH 77/

The MU9C8358L outputs /W (read/write select) to control

the direction of data flow between the MU9C8358L and

the LANCAM. If /W is LOW at the falling edge of /E, the

MU9C8358L outputs data on the DQ[15:0] bus for the

LANCAM as input. When /W is HIGH at the falling edge

of /E, the LANCAM outputs data on the DQ[15:0] bus to

the MU9C8358L as input.

5HY 



Share Link: