8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.3 Definition of Real-Time Wait Symbols
Table 12. Real-time Wait Timing Symbol Definitions
Signals
A Address
D Data
C WCLK
Y WAIT#
W WR#
R RD#/PSEN#
Conditions
L Low
X Hold
V Setup
6.3.4 External Bus Cycles, Real-Time Wait States
WCLK
ALE
RD#/PSEN#
WAIT#
P0
P2
State 1
State 2
State 3
State 1 (next cycle)
TRLYX max
TRLYX min
TRLYV
TCLYV
TCLYX min
TCLYX max
RD#/PSEN# stretched
A7:0
D7:0
A15:8
stretched
stretched
A7:0
A15:8
A5000-02
Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)
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